Semiconductor integrated circuit device and its manufacturing method

ABSTRACT

A semiconductor integrated circuit device has a plurality of rows of pillars, each row being composed of semiconductor pillars and insulator pillars alternately arranged in one direction with no gap therebetween, a plurality of nonvolatile memory elements provided individually in the plurality of semiconductor pillars, the plurality of nonvolatile memory elements having control gate electrodes provided over side surfaces of said semiconductor pillars along the one direction via gate insulating films, drain regions provided in upper surface portions of the semiconductor pillars, and source regions provided in bottom surface portions of the semiconductor pillars, and lines including the respective control gate electrodes of the plurality of nonvolatile memory elements and provided along the one direction over the side surfaces of the rows of pillars along the one direction.

TECHNICAL FIELD

The present invention relates to a semiconductor integrated circuitdevice and its manufacture; and, more particularly, the presentinvention relates to a technique which is effective when applied to asemiconductor integrated circuit device having a nonvolatile memoryelement to which electrical erasing and writing of data can beperformed.

BACKGROUND OF THE INVENTION

In recent years, a nonvolatile memory device called a flash EEPROM(Electrically Erasable Programmable Read Only Memory), in which datastored therein can be erased electrically simultaneously in specifiedunits and in which data can be written electrically, has drawn increasedattention as a memory device for storing data and data for programcomposition. The flash EEPROM (hereinafter referred to as a flashmemory) has a memory cell composed of an electrically erasable andwritable nonvolatile memory element, so that it is possible to erasedata or data for program composition once written in the memory celltherefrom and rewrite (program) new data or data for program compositionin the memory cell.

Conventionally, the accumulation of a charge in a flash memory has beenperformed by accumulating electrons in a floating gate electrode(floating gate electrode) that is composed of a polysilicon film and iselectrically insulated from surrounding elements. This electronaccumulating operation, i.e., a so-called write operation, is performednormally by injecting hot electrons, while an erase operation whichreleases the accumulated electrons to the outside of the floating gateelectrode is performed by using a tunnel current passing through a gateoxide film. When the writing and erasing are repeated, a charge trap isformed in the gate oxide film so that the density of the surface statesincreases at the interface between the substrate and the gate oxidefilm. In particular, the former has the essential problem of degradingthe charge retention property, i.e., the retention property after therewriting.

As a method of eliminating the foregoing problem, a system has beenproposed which uses a nonconductive charge trap film for chargeaccumulation in an EEPROM. Examples of such a system are disclosed inU.S. Pat. Nos. 5,768,192, 5,966,603, 6,011,725, and 6,180,538 and in“Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a Real Challenge toFloating Gate Cell”, B. Eitan et al., International Conference On SolidState Devices and Materials, Tokyo, 1999.

As shown in FIG. 39 (diagrammatic cross-sectional view of a cell), e.g.,the system disclosed in U.S. Pat. No. 5,768,192 uses, as a gateinsulating film, a multilayer film having a so-called ONO(Oxide/Nitride/Oxide) structure in which a silicon nitride film 113 isinterposed between insulating films 112 and 114 each composed of asilicon oxide film or the like. The transistor is turned ON by applying0 V to a source 117 and a proper positive voltage to each of a drain 116and a control gate 115, whereby hot electrons generated in the vicinityof the drain 116 are injected such that the electrons are trapped in thesilicon nitride film 113, and writing is performed. In this chargeaccumulating system, electron traps in the silicon nitride film 113 arediscontinuous and discrete compared with those in a system whichaccumulates a charge in a polysilicon film which is a continuousconductive film. Accordingly, there is no situation in which theaccumulated charge will entirely dissipate even when a charge leakagepath, such as a pinhole, occurs in a part of the oxide film 112, so thatthe system features an inherently reliable retention property.

On the other hand, U.S. Pat. No. 6,011,725 discloses a so-calledmulti-valued cell technique which independently controls chargeaccumulation in two places in the vicinity of the drain 116 and in thevicinity of the source 117 by using the locality of hot electroninjection and thereby implements 2-bit information in one cell, as shownin FIG. 40 (diagrammatic cross-sectional view of a cell).

A method of forming an ONO film is also disclosed in U.S. Pat. No.5,966,603, which forms an ONO structure by, e.g., forming an ONmultilayer film on a substrate, and then oxidizing an upper portion of asilicon nitride film, or, by forming an ONO multilayer film on asubstrate, and then adding an oxidation step to introduce oxygen intothe silicon nitride film, thereby improving the retention property ofthe memory cell.

A method of forming an ONO film by RTCVP (Rapid Thermal Chemical VaporDeposition) is also claimed in U.S. Pat. No. 6,180,538, in which thetemperature for the deposition of an oxide film is 700 to 800° C. andthe thickness of the oxide film is 5 to 15 nm.

SUMMARY OF THE INVENTION

In the foregoing well-known example, such as disclosed in U.S. Pat. No.5,966,603 or “Can NROM, a 2-bit, Trapping Storage NVM Cell, Give a RealChallenge to Floating Gate Cell”, B. Eitan et al., InternationalConference on Solid State Devices and Materials, Tokyo, 1999, a cellmode of the virtual ground type is disclosed. In the arrangement ofcells shown in each of FIG. 41 (diagrammatic plan view of a memory cellarray portion), FIG. 42 (diagrammatic cross-sectional view along thedirection of the gate length of a cell), and FIG. 43 (diagrammaticcross-sectional view along the direction of the gate width of a cell),diffusion layer regions composing the drain 116 and the sources 117 arearranged in stripes and oxide films 118 for retaining insulation fromthe control gate electrodes 115 are provided on the upper portionsthereof, and the control gate electrode 115 are disposed in anorthogonal relation to the source/drain direction. The oxide films 112,the nitride films 113, and the oxide films 114 are disposed between thechannel regions of a semiconductor substrate 111 interposed between thedrain 116 and the sources 117 and the control gate electrodes 115. Asshown in FIG. 41, the current path in write and read operations causesthe adjacent diffusion layers to operate as the sources 117 and thedrain 116, and a channel current in each of the cells flows in adirection parallel to the control gate electrodes 115. The area of thecell is designed such that the pitch of the sources/drain is double theminimum dimension F, and the pitch of the control gates is also doublethe minimum dimension F, i.e., 2F×2F=4F² is satisfied. For example, a0.2-μm technology allows the implementation of an extremely small cellarea of 4F²=0.16 μm².

However, the foregoing memory cells have several problems.

A first problem is that each of the conventional cells cannot bedesigned to allow a large read current. As shown in FIG. 41, the channelwidth W of the cell is defined by the width of each of the control gateelectrodes 115, and the channel length L thereof is defined by thedistance between the source 117 and the drain 116, so that a structuralconstant W/L determining the channel current becomes W/L=F/F=1, so thatthe read current does not increase even when the cell is miniaturized.Accordingly, the read current cannot increase unless other structuralconstants or the effective thickness of the multilayer film consistingof the oxide film 112, the nitride film 113, and the oxide film 114 isreduced. This causes the problems of deterioration of the access speedand a lowering of the margin for misoperation of a sense amplifier.

A second problem is the problem of so-called read disturb, which occurswhen an increase in the read current is intended by increasing thecontrol gate voltage during a read operation in an attempt to solve thefirst problem. As shown in FIGS. 42 and 43, this phenomenon is caused bythe extraction of electrons trapped in the nitride film of a cell in awritten state toward the control gate due to the control gate voltagewhen reading is performed with respect to the cell. This leads to a datainversion failure. The time period of the disturbance resulting from theextraction of the trapped electrons should be determined by assumingcontinuous reading over ten years at the maximum. By increasing thethickness of the oxide film 114 overlying the nitride film 113, theresistance to the disturbance can be enhanced, but the read currentpresenting the first problem is further reduced disadvantageously.

A third problem is that it is difficult to adjust the cell area to 4 F²or less because the control gate electrodes have been formed bypatterning a conductive film by using an etching mask. As a result ofexamining well-known examples associated with this problem, it was foundthat Japanese Unexamined Patent Publication No. HEI 6(1994)-13628discloses a technology related to a reduction in cell area. As describedin the paragraph number [0020] of this publication, the technologydisclosed in the publication “places a channel formation region betweena source and a drain, which has been disposed conventionally in atwo-dimensional orientation, in a vertical orientation and therebyreduces the area of the portion occupied conventionally. The fundamentalof the present invention lies in the formation of a projecting portionon a semiconductor substrate, the use of the side surfaces thereof aschannel formation regions, the use of the top portion thereof as one ofimpurity regions (source or drain), the provision of the other impurityregions at the bottom portions thereof, and the formation of gateelectrodes on the side surfaces of the channel formation regions.” It isalso described in the paragraph number [0067] of this publication that“Thereafter, a coating 309 for forming gate lines (control gates) isformed . . . . After that, the coating 309 is removed by anisotropicetching except for the portion thereof covering the side surfaces of theprojecting portion so that gate lines 310 are formed. It is to be notedthat the gate lines extend along the side surfaces of the projectingportion. The present invention features the formation of the gateelectrodes which does not involve a mask process.” Therefore, the cellarea can be adjusted to 4F² or less by using the technology disclosed inthis publication.

According to the technology disclosed in the above-referencedpublication, however, a semiconductor is present in the isolation regionof the projecting portion, since the formation of the isolation regionof the projecting portion is performed by using an oxide film formed bya thermal oxidation process, and, in addition, the gate lines extendalong the side surfaces of the projecting portion. Briefly, theisolation region of the projection has a MOS structure using asemiconductor in the isolation region of the projecting portion as achannel formation region, using the oxide film formed in the isolationregion of the projecting portion as a gate insulating film, and usingthe gate line extending along the side surface of the projecting portionas a gate electrode. Consequently, if a voltage is applied to the gateline, a parasitic channel is formed in the side surface of thesemiconductor in the isolation region of the projecting portion, andthis causes a situation where electrical connection is provideddisadvantageously between the respective channel formation regions ofadjacent nonvolatile memory elements. Such a situation serves as afactor which causes a data erase failure, a data write failure, or adata read failure, so that the electric reliability of the flash memoryis degraded.

It is therefore an object of the present invention to provide asemiconductor integrated circuit device which allows a significantincrease in the read current for a nonvolatile memory using anonconductive trap film as a charge accumulation region and allows theelimination of a read failure due to data inversion caused by a readdisturb condition.

Another object of the present invention is to provide a device structurewhich allows easy reduction of the cell area of a nonvolatile memoryusing a nonconductive charge trap film as a charge accumulation region.

Still another object of the present invention is to provide a technologywhich allows an improvement in the electrical reliability of asemiconductor integrated circuit device having a nonvolatile memoryelement to which electrical writing and erasing of data can beperformed.

The above and other objects and novel features of the present inventionwill become apparent from the description provided in the presentspecification and the accompanying drawings. The following is a briefdescription of representative aspects of the present invention disclosedin the present application.

(1) A semiconductor integrated circuit device comprising: a plurality ofrows of pillars, each row being composed of semiconductor pillars andinsulator pillars alternately arranged in one direction with no gaptherebetween; a plurality of nonvolatile memory elements providedindividually in the plurality of semiconductor pillars, the plurality ofnonvolatile memory elements having control gate electrodes provided overside surfaces of the semiconductor pillars along the one direction viagate insulating films, drain regions provided in upper surface portionsof the semiconductor pillars, and source regions provided in bottomsurface portions of the semiconductor pillars; and lines including therespective control gate electrodes of the plurality of nonvolatilememory elements and provided along the one direction over the sidesurfaces of the rows of pillars along the one direction.

(2) A semiconductor integrated circuit device comprising electricallywritable nonvolatile memory elements each having, in a semiconductorregion: a source region; a drain region; a channel formation regioninterposed between the source region and the drain region; and a controlgate electrode, wherein two of the channel formation regions aredisposed independently over respective opposing side surfaces of each ofrectangular-parallelepiped semiconductor pillars, the drain regionconnected to the two channel formation regions is formed in an upperportion of the rectangular-parallelepiped semiconductor pillar,isolation regions are disposed over side surface portions adjacent tothe channel formation regions, a first insulating film is providedbetween each of the channel formation regions and the control gateelectrode, a nonconductive charge trap film is provided over the firstinsulating film, and a second insulating film is provided over thenonconductive charge trap film.

(3) A semiconductor integrated circuit device as defined in theforegoing paragraph (2), wherein writing is performed by placing thesource region at a ground potential, giving a proper positive potentialto each of the drain region and the control gate electrode to turn ONthe channel formation regions, and injecting hot electrons generated inthe vicinity of the drain region such that the electrons are trapped inthe nonconductive charge trap film and erasing is performed by giving aproper negative potential and a proper positive potential to the controlgate electrode and the drain region, respectively, and therebyextracting the electrons trapped in the nonconductive charge trap filmto the semiconductor region by using a tunnel current flowing in thefirst insulating film.

(4) A semiconductor integrated circuit device as defined in theforegoing paragraph (2), wherein the first insulating film is a siliconoxide film, the nonconductive charge trap film is a silicon nitridefilm, and the second insulating film is a silicon oxide film.

(5) A semiconductor integrated circuit device as defined in theforegoing paragraph (2), wherein the first insulating film is a siliconoxide film, the nonconductive charge trap film is a metal oxide film,and the second insulating film is a silicon oxide film.

(6) A semiconductor integrated circuit device comprising electricallywritable nonvolatile memory elements each having, in a semiconductorregion: a source region; a drain region; a channel formation regioninterposed between the source region and the drain region; and a controlgate electrode, wherein two of the channel formation regions aredisposed independently over respective opposing side surfaces of each ofrectangular-parallelepiped semiconductor pillars, the drain regionconnected to the two channel formation regions is formed in an upperportion of the rectangular-parallelepiped semiconductor pillar,isolation regions are disposed over side surface portions adjacent tothe channel formation regions, a first insulating film is providedbetween each of the channel formation regions and the control gateelectrode, a semiconductor film is provided on the first insulatingfilm, a nonconductive charge trap film is provided over the firstinsulating film, a second insulating film is provided over thenonconductive charge trap film, and electrons are trapped primarily in acharge trap level at an interface between the semiconductor film and thenonconductive charge trap film.

(7) A semiconductor integrated circuit device as defined in theforegoing paragraph (6), wherein writing is performed by placing thesource region at a ground potential, giving a proper positive potentialto each of the drain region and the control gate electrode to turn ONthe channel formation regions, and injecting hot electrons generated inthe vicinity of the drain region such that the electrons are trappedprimarily in a charge trap level at an interface between thesemiconductor film and the nonconductive charge trap film and erasing isperformed by giving a proper negative potential and a proper positivepotential to the control gate electrode and the drain region,respectively, and thereby extracting the trapped electrons to thesemiconductor region by using a tunnel current flowing in thesemiconductor film and the first insulating film.

(8) A semiconductor integrated circuit device as defined in theforegoing paragraph (6), the first insulating film is a silicon oxidefilm, the semiconductor film is a polysilicon film, the nonconductivecharge trap film is a silicon nitride film, and the second insulatingfilm is a silicon oxide film.

(9) A semiconductor integrated circuit device as defined in theforegoing paragraph (6), the first insulating film is a silicon oxidefilm, the semiconductor film is a polysilicon film, the nonconductivecharge trap film is a metal oxide film, and the second insulating filmis a silicon oxide film.

(10) A method for manufacturing a semiconductor integrated circuitdevice, the method comprising at least the steps of: alternatelyforming, over a semiconductor substrate, trenched isolation regions andsemiconductor active regions in stripes, performing etching with respectto the semiconductor active regions and the trenched isolation regionsin succession by using, as a mask, resist film patterns formed instripes in directions orthogonal to the trenched isolation regions andsemiconductor active regions in stripes to formrectangular-parallelepiped semiconductor pillars andrectangular-parallelepiped isolation regions; forming channel formationregions in respective side surface portions of each of therectangular-parallelepiped semiconductor pillars, depositing amultilayer film composed of a first oxide film, a polysilicon film, anitride film, and a second oxide film over each of the channel formationregions, and forming word lines composed of side spacers each made of aconductive film; and forming a drain region in an upper portion of eachof the rectangular-parallelepiped semiconductor pillars.

(11) A method for manufacturing a semiconductor integrated circuitdevice, the method comprising at least the steps of: alternatelyforming, over a semiconductor substrate, trenched isolation regions andsemiconductor active regions in stripes, performing etching with respectto the semiconductor active regions and the trenched isolation regionsin succession by using, as a mask, resist film patterns formed instripes in directions orthogonal to the trenched isolation regions andsemiconductor active regions in stripes to formrectangular-parallelepiped semiconductor pillars andrectangular-parallelepiped isolation regions; forming channel formationregions in respective side surface portions of each of therectangular-parallelepiped semiconductor pillars, depositing amultilayer film composed of a first oxide film, a polysilicon film, anitride film, and a second oxide film over each of the channel formationregions, and forming word lines composed of side spacers each made of aconductive film; and forming a drain region in an upper portion of eachof the rectangular-parallelepiped semiconductor pillars.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagrammatic plan view showing the structure of a memorycell array portion in a flash memory representing Embodiment 1 of thepresent invention;

FIG. 2 is an equivalent circuit diagram of the memory cell array portionof FIG. 1;

FIG. 3 is a diagrammatic cross-sectional view taken along the line A—Aof FIG. 1;

FIG. 4 is a diagrammatic cross-sectional view obtained by enlarging apart of FIG. 1;

FIG. 5 is a diagrammatic cross-sectional view taken along the line B—Bof FIG. 1;

FIG. 6 is a diagrammatic cross-sectional view taken along the line C—Cof FIG. 1;

FIG. 7 is a diagrammatic plan view of the flash memory representingEmbodiment 1 of the present invention as seen in a manufacturing processstep therefor;

FIG. 8 is a diagrammatic cross-sectional view taken along the line B—Bof FIG. 7;

FIG. 9 is a diagrammatic plan view of the flash memory as seen in amanufacturing process step subsequent to that of FIG. 7;

FIG. 10( a) is a diagrammatic cross-sectional view taken along the lineA—A of FIG. 9, and FIG. 10( b) is a diagrammatic cross-sectional viewtaken along the line C—C of FIG. 9;

FIG. 11 is a diagrammatic plan view of the flash memory as seen in amanufacturing process step subsequent to that of FIG. 9;

FIG. 12( a) is a diagrammatic cross-sectional view taken along the lineA—A of FIG. 11, and FIG. 12( b) is a diagrammatic cross-sectional viewtaken along the line C—C of FIG. 11;

FIG. 13 is a diagrammatic plan view of the flash memory as seen in amanufacturing process step subsequent to that of FIG. 11;

FIG. 14( a) is a diagrammatic cross-sectional view taken along the lineA—A of FIG. 13, and FIG. 14( b) is a diagrammatic cross-sectional viewtaken along the line C—C of FIG. 13;

FIG. 15 is a diagrammatic cross-sectional view of the flash memory asseen in a manufacturing process step subsequent to that of FIG. 13;

FIG. 16 is a diagrammatic cross-sectional view of the flash memory asseen in a manufacturing process step subsequent to that of FIG. 15;

FIG. 17 is a diagrammatic plan view of the flash memory as seen in amanufacturing process step subsequent to that of FIG. 16;

FIG. 18( a) is a diagrammatic cross-sectional view taken along the lineA—A of FIG. 17, and FIG. 18( b) is a diagrammatic cross-sectional viewtaken along the line C—C of FIG. 17;

FIG. 19 is a diagrammatic cross-sectional view of the flash memory asseen in a manufacturing process step subsequent to that of FIG. 17;

FIG. 20 is a diagrammatic cross-sectional view of the flash memory asseen in a manufacturing process step subsequent to that of FIG. 19;

FIG. 21 is a diagrammatic cross-sectional view of the flash memory asseen in the manufacturing process step subsequent to that of FIG. 20;

FIG. 22 is a diagrammatic cross-sectional view of the flash memory asseen in the manufacturing process step subsequent to that of FIG. 21;

FIG. 23 is a diagrammatic plan view showing the structure of aperipheral region of a memory cell array portion in a flash memoryrepresenting Embodiment 2 of the present invention;

FIG. 24 is a diagrammatic plan view showing the state in which a part ofFIG. 23 has been removed;

FIG. 25 is a diagrammatic cross-sectional view of a flash memoryrepresenting Embodiment 3 of the present invention as seen in amanufacturing process step therefor;

FIG. 26 is a diagrammatic cross-sectional view of the flash memory asseen in a manufacturing process step subsequent to that of FIG. 25;

FIG. 27 is a diagrammatic cross-sectional view of the flash memory asseen in a manufacturing process step subsequent to that of FIG. 26;

FIG. 28 is a diagrammatic cross-sectional view of the flash memory asseen in a manufacturing process step subsequent to that of FIG. 27;

FIG. 29 is a diagrammatic cross-sectional view of the flash memory asseen in a manufacturing process step subsequent to that of FIG. 28;

FIG. 30 is a diagrammatic cross-sectional view of the flash memory asseen in a manufacturing process step subsequent to that of FIG. 29;

FIG. 31 is a diagrammatic cross-sectional view of the flash memory asseen in a manufacturing process step subsequent to that of FIG. 30;

FIG. 32 is a diagrammatic cross-sectional view of the flash memory asseen in a manufacturing process step subsequent to that of FIG. 31;

FIG. 33 is a diagrammatic cross-sectional view of the flash memory asseen in a manufacturing process step subsequent to that of FIG. 32;

FIG. 34 is a diagrammatic cross-sectional view of the flash memory asseen in a manufacturing process step subsequent to that of FIG. 33;

FIG. 35 is a diagrammatic plan view showing the structure of a memorycell array portion in a flash memory representing Embodiment 4 of thepresent invention;

FIG. 36( a) is a diagrammatic cross-sectional view taken along the lineC–C′ of FIG. 35, and FIG. 36( b) is a diagrammatic cross-sectional viewtaken along the line D—D of FIG. 35;

FIG. 37 is a diagrammatic plan view showing the structure of a flashmemory representing Embodiment 5 of the present invention;

FIG. 38 is a diagrammatic plan view showing the structure of a flashmemory representing Embodiment 6 of the present invention;

FIG. 39 is a diagrammatic cross-sectional view showing the structure ofa first cell representing conventional technology;

FIG. 40 is a diagrammatic cross-sectional view showing the structure ofa second cell representing conventional technology;

FIG. 41 is a diagrammatic plan view showing the structure of a thirdcell representing conventional technology;

FIG. 42 is a diagrammatic cross-sectional view taken along the directionof the gate length of the third cell shown in FIG. 41;

FIG. 43 is a diagrammatic cross-sectional view taken along the directionof the gate width of the third cell shown in FIG. 41;

FIG. 44 is a diagrammatic plan view of the peripheral region of thememory cell array portion in the flash memory shown in FIGS. 23 and 24as seen in a manufacturing process step therefor;

FIG. 45 is a diagrammatic plan view of the memory cell array portion asseen in a manufacturing process step subsequent to that of FIG. 44;

FIG. 46 is a diagrammatic plan view of the memory cell array portion asseen in the manufacturing process step subsequent to that of FIG. 45;

FIG. 47 is a diagrammatic plan view of the memory cell array portion asseen in the manufacturing process step subsequent to that of FIG. 46;

FIG. 48 is a diagrammatic plan view of the memory cell array portion asseen in the manufacturing process step subsequent to that of FIG. 47;

FIG. 49 is a diagrammatic plan view of the memory cell array portion asseen in the manufacturing process step subsequent to that of FIG. 48;and

FIG. 50 is a diagrammatic plan view of the memory cell array portion asseen in the manufacturing process step subsequent to that of FIG. 49.

BEST MODE FOR CARRYING OUT THE INVENTION

Referring to the drawings, various embodiments of the present inventionwill be described in detail below. Throughout all of the drawings, partshaving the same function are designated by the same reference numerals,and a repeated description thereof will be omitted.

EMBODIMENT 1

FIG. 1 is a diagrammatic plan view showing the structure of a memorycell array portion in a flash memory representing Embodiment 1 of thepresent invention.

FIG. 2 is an equivalent circuit diagram of the memory cell array portionof FIG. 1.

FIG. 3 is a diagrammatic cross-sectional view taken along the line A—Aof FIG. 1.

FIG. 4 is a diagrammatic cross-sectional view obtained by enlarging apart of FIG. 1.

FIG. 5 is a diagrammatic cross-sectional view taken along the line B—Bof FIG. 1.

FIG. 6 is a diagrammatic cross-sectional view taken along the line C—Cof FIG. 1.

In the memory cell array portion MSA of the flash memory in the presentembodiment, a plurality of word lines WL and a plurality of data linesBL extend, as shown in FIGS. 1 and 2. The plurality of word lines WLextend in the Y-direction and are arranged at a given spacing in theX-direction orthogonal to the Y-direction. The plurality of data linesBL extend in the X-direction and are arranged at a given spacing in theY-direction. In the memory cell array portion, a plurality of memorycells MS, as shown in FIGS. 1 and 2, are arranged as a matrix (in the X-and Y-directions). In the memory cell array portion MSA, a plurality ofrows of pillars 20 extending in the Y-direction are arranged at a givenspacing in the X-direction.

As shown in FIGS. 1 to 6, the rows of pillars 20 are composed of aplurality of semiconductor pillars 5 and a plurality of insulatorpillars 4 which are alternately arranged in the Y-direction with no gaptherebetween. The semiconductor pillars 5 and the insulator pillars 4are provided on a principal surface of a p-type semiconductor substrate1 that is composed of, e.g., single-crystal silicon. The semiconductorpillars 5 and the insulator pillars 4 are formed primarily by performinga trenching process with respect to the semiconductor substrate 1, whichprocess will be described later in detail. In the present embodiment,each of the semiconductor pillars 5 and the insulator pillars 4 isconfigured as, e.g., a rectangular parallelepiped. Each of the insulatorpillars 4 is formed of, e.g., a silicon oxide film (insulating film) 3.

The memory cells MS are composed of nonvolatile memory elements Q formedin the individual semiconductor pillars 5. As shown in FIGS. 3 and 4,the nonvolatile memory elements Q are principally constructed to havechannel formation regions CN, gate insulating films GI, control gateelectrodes 11, source regions, and drain regions. The channel formationregions CN are provided in the side surfaces of the semiconductorpillars 5 along the Y-direction. The gate insulating films GI areprovided on the channel formation regions CN (on the side surfaces ofthe semiconductor pillars 5). The control gate electrodes 11 are formedon the gate insulating films GI. The drain regions are provided in theupper surface portions of the semiconductor pillars 5, while the sourceregions are provided in the bottom surface regions of the semiconductorpillars 5.

Although the gate insulating films GI are not limited thereto, each ofthem is formed of a multilayer film 9 in which a silicon oxide film 9 a,a silicon nitride film 9 b, and a silicon oxide film 9 c are stackedsuccessively in layers on the side surface of the semiconductor pillar5. The silicon nitride film 9 b is a film for discretely accumulatingcharge therein. Accordingly, electron traps are formed discontinuouslyand discretely in the silicon nitride film 9 b. Thus, each of the gateinsulating films GI is composed of a multilayer film including a filmfor discretely accumulating a charge therein.

The control gate electrodes 11 are composed of parts of word lines WLextending along the side surfaces of the rows of pillars 20 along theY-direction. The word lines WL have been formed by self alignment withthe rows of pillars 20 and are processed into side spacers. Each of theword lines WL is formed of a polysilicon film into which, e.g., animpurity for reducing the resistance value (such as As) has beenintroduced.

The drain regions are composed of n-type semiconductor regions 12provided in the respective upper surface portions of the semiconductorpillars 5, while the source regions are composed of n-type semiconductorregions 8 provided in the bottom surface portions of the semiconductorpillars 5. The n-type semiconductor regions 8 are provided in the bottomsurface portions of trenches primarily defining the widths of the rowsof pillars 20 in the X-direction to compose the source lines extendingcontinuously along the Y-direction. In short, the source regions arecomposed of parts of the source lines extending continuously along therows of pillars 20.

As shown in FIGS. 3 and 4, each of the semiconductor pillars 5 isprovided with two nonvolatile memory elements Q. Of the two nonvolatilememory elements Q, one has the channel formation region CN thereofprovided on one of the two opposing side surfaces of the semiconductorpillar 5, while the other nonvolatile memory element Q has the channelformation region CN thereof provided on the other of the two sidesurfaces. Each of the nonvolatile memory elements Q has a channel lengthL defined by the height (an amount of protrusion) of the semiconductorpillar 5 and a channel width W defined by the width of the semiconductorpillar 5 along the Y-direction.

As shown in FIGS. 5 and 6, each of the semiconductor pillars 5 and theinsulator pillars 4 is formed to have substantially the same processingdimensions. In the rows of pillars 20, the plurality of semiconductorpillars 5 are dielectrically isolated from each other by the insulatorpillars 4. The insulator pillars 4 are provided to reach the n-typesemiconductor regions 8, while the plurality of n-type semiconductorregions 12 provided in the respective upper surface portions of theplurality of semiconductor pillars 5 are dielectrically isolated fromeach other by the insulator pillars 4 provided between the semiconductorpillars 5.

As shown in FIGS. 1 to 6, the semiconductor pillars 5 and insulatorpillars 4 of each of the rows of pillars 20 are covered with aninsulating film 13 provided on the principal surface of thesemiconductor substrate 1. The portions of the insulating film 13opposing the upper surface portions of the semiconductor pillars 5 areprovided with openings 14. In the openings 14, insulating films 16 eachcomposed of a silicon nitride film are provided as side spacers alongthe inner wall surfaces of the openings 14. In openings 17 defined bythe insulating films 16, contact plugs 18 connected electrically to then-type semiconductor regions 12 as the drain regions have been buried.To the contact plugs 18, bit lines BL have been connected. Consequently,the n-type semiconductor regions 12 as the drain regions provided in theupper surface portions of the semiconductor pillars 5 are connectedelectrically to the bit lines BL via the contact plugs 18.

In the present embodiment, the memory cells MS (nonvolatile memoryelements Q) have the drain regions disposed in the upper surface regionsof the rectangular-parallelepiped semiconductor pillars 5 dielectricallyisolated from each other by the rectangular-parallelepiped insulatorpillars 4, have the channel formation regions CN and the multilayerfilms 9 consisting of the silicon oxide films (first oxide films) 9 a,the silicon nitride films (nonconductive charge trap films) 9 b, and thesilicon oxide films (second oxide films) 9 c on the side surfaceportions of the semiconductor pillars 5, have the control gateelectrodes (control gate electrodes) 11 composed of the polysiliconfilms and disposed as side spacers outside the silicon oxide films(second oxide films) 9 c, and have the openings (contact holes) 17 tothe drain regions and the bit lines BL above the upper surface regionsof the rectangular-parallelepiped semiconductor pillars 5, as shown inFIGS. 1 to 6. Each of the memory cells MS is constructed as anonvolatile memory element which performs writing by giving a properpositive potential to each of the drain region and the control gateelectrode 11 so as to turn ON the channel formation region CN and injecthot electrons generated in the vicinity of the drain region such thatthey are trapped in the nonconductive silicon nitride film (charge trapfilm) 9 b, while performing erasing by giving a proper negativepotential and a proper positive potential to the control gate electrode11 and the drain region, respectively, and thereby extracting theelectrons trapped in the nonconductive silicon nitride film (charge trapfilm) 9 b to the drain region by using a tunnel current flowing in thesilicon oxide film (first oxide film) 9 a.

In the direction along the A—A line (X-direction), the silicon oxidefilms (first oxide films) 9 a, the nonconductive charge trap films 9 b,the silicon oxide films (second oxide films) 9 c, and the control gateelectrodes 11 shaped like side spacers are disposed successively on theside surface portions of the rectangular-parallelepiped semiconductorpillars 5 in such a manner as to cover the outer circumference, whilethe source regions composed of the n-type semiconductor regions 8 aredisposed in the lower portions of the rectangular-parallelepipedsemiconductor pillars 5 and the drain regions composed of the n-typesemiconductor regions 12 are disposed in the respective upper portionsthereof. In the direction along the B—B line (Y-direction), therectangular-parallelepiped semiconductor pillars 5 are isolated fromeach other by the insulating films 3 and the drain regions are connectedto the bit lines BL via the contact plugs 18.

In the memory cells MS according to the present embodiment, each of therectangular-parallelepiped semiconductor pillars 5 is disposed to have aminimum dimension F×F, as shown in FIG. 1. The width of the isolationdisposed between the adjacent rectangular-parallelepiped semiconductorpillars 5 also has a minimum dimension F. Accordingly, the planar areaof each of the rectangular-parallelepiped semiconductor pillars 5 is2F×2F=4F² Since two cells can be disposed in one semiconductor pillar 5,the memory cell MS according to the present embodiment can be designedto have a small unit cell area of 2F². The channel width W of the memorycell MS according to the present embodiment is equal to the width F ofthe rectangular-parallelepiped semiconductor pillar 5 and the channelwidth L thereof is determined by the height of therectangular-parallelepiped semiconductor pillar 5. When the height ofthe rectangular-parallelepiped semiconductor pillar 5 is assumed to beF, a structural constant W/L determining the channel current becomesF/F=1. This indicates that the same read current can be retainedirrespective of the fact that the cell area of the memory cell MSaccording to the present embodiment is one half of the cell area of aconventional cell, which is 4F², and therefore the effectiveness of thepresent embodiment is established.

In the present embodiment, the plurality of semiconductor pillars 5 ofthe rows of pillars 20 are dielectrically isolated from each other bythe insulator pillars 4 provided therebetween. Consequently, nosemiconductor is present in the isolation regions of the rows of pillars20, so that no parasitic channel is formed in the isolation regions evenwhen the word lines WL extending continuously along the side surfaces ofthe rows of pillars 20 in the Y-direction are formed on the sidesurfaces. This allows the suppression of a data erase failure, a datawrite failure, and a data read failure resulting from the formation of aparasitic channel and an improvement in the electrical reliability ofthe flash memory. Even when the memory size is reduced throughminiaturization, a failure resulting from the formation of a parasiticchannel does not occur and the reliability can be improved.

A description will be given next of the manufacture of the flash memorywith reference to FIGS. 7 to 22.

First, as shown in FIGS. 7 and 8, active regions 5 a and trenchedisolation regions 4 a are formed in stripes on the semiconductorsubstrate 1. At this time, the active regions 5 a are isolated from eachother by the trenched isolation regions 4 a and surface oxide films 6have been grown on the upper portions of the active regions 5 a. Thetrenched isolation regions 4 a are formed by forming trenches 2 in thesemiconductor substrate 1, forming the insulating film 3 in such amanner as to fill in the trenches 2, and then planarizing the surface ofthe insulating film 3 by CMP.

In short, trenched patterns 4 a in stripes having, e.g., widths andspacings of the minimum dimension F in the Y-direction and extending inthe X-direction are formed on the semiconductor substrate 1. Then, aninsulating film composed of, e.g., a silicon oxide film is deposited byCVD on the principal surface of the semiconductor substrate 1 includingthe inside of each of the trenched patterns 4 a. Then, the insulatingfilm is planarized by, e.g., polishing such as CMP, whereby theinsulating film is buried in each of the trenched patterns 4 a to formthe trenched isolation regions 4 a in stripes. Accordingly, each of thewidths and spacings of the active regions 5 a in the Y-direction iscomposed of, e.g., the minimum processing dimension F.

Next, as shown in FIGS. 9 and 10, resist patterns RM in stripes areformed in a direction orthogonal to the direction in which the activeregions 5 a are arranged. By using the resist patterns RM as a mask, theactive regions 5 a are etched selectively to form therectangular-parallelepiped semiconductor pillars 5. Then, as shown inFIGS. 11 and 12, the trenched isolation regions 4 a are etched by usingthe resist patterns RM as a mask to form the rectangular-parallelepipedinsulator pillars 4. Each of the resist patterns RM has the widths andspacings of the minimum dimension F in, e.g., the X-direction.Accordingly, each of the semiconductor pillars 5 and the insulatorpillars 4 has the width and spacing of the minimum dimension F in theX-direction and in the Y-direction.

Next, as shown in FIGS. 13 and 14, the source regions composed of then-type semiconductor regions 8 are formed by ion implantation of animpurity such as arsenic As or phosphorus P using the resist patterns RMas a mask.

Next, as shown in FIG. 15, the multilayer film 9 consisting of thesilicon oxide film (first oxide film) 9 a, the nitride film 9 b, and thesilicon oxide film (second oxide film) 9 c is deposited on the sidesurface portions of the semiconductor pillars 5. Then, as shown in FIG.16, a polysilicon film 10 is formed. Thereafter, anisotropic etchingsuch as RIE is performed with respect to the polysilicon film 10 to formthe control gate electrodes 11 (word lines WL) composed of thepolysilicon films shaped like side spacers as shown in FIGS. 17 and 18.

Next, an impurity is introduced by ion implantation into the upperportions of the semiconductor pillars 5 so that the drain regionscomposed of the n-type semiconductor regions 12 are formed, as shown inFIG. 18.

Next, as shown in FIG. 19, the insulating film 13 is formed. Then, asshown in FIG. 20, the openings 14 for exposing the upper portions of thesemiconductor pillars 5 are formed in the insulating film 13.

Next, as shown in FIG. 21, an insulating film 15 is formed over thesubstrate including the inside of each of the openings 14. Thereafter,anisotropic etching such as RIE is performed with respect to theinsulating film 15 to form the insulating films 16 shaped like sidespacers (sidewall spacers) in the inner walls of the openings 14, asshown in FIG. 22.

Next, the contact plugs 18 to be connected to the drain regions areformed in the openings (connection holes) 17 defined by the sidewallspacers 16, i.e., on the upper surfaces of the semiconductor pillars 15.Thereafter, the bit lines BL are formed in a direction orthogonal to thedirection in which the control gate electrodes 11 are arranged, wherebythe state shown in FIGS. 1 to 6 are obtained.

In the process steps for manufacturing the memory cells according to thepresent invention, conventionally usable manufacturing techniques areused, which indicates that the memory cells according to the presentinvention can be manufactured by using such conventional techniques.

EMBODIMENT 2

The present embodiment pertains to the connection of electrodes to thecontrol gate electrodes formed as side spacers in the memory cellsaccording to the present application. In FIGS. 23 and 24, plan views ofthe nonvolatile memory cells according to the present invention areshown schematically. In the drawings, an electrode connecting structureto the control gate electrodes at the edge portions of a memory array isshown, in which rectangular-parallelepiped semiconductor pillars 41 arearranged and trenched isolation regions (insulator pillars) 42 areformed such that every second of them is different in length at the edgeportions of the memory array. In the processing of control gateelectrodes 45 into side spacers, regions from which the control gateelectrodes 45 are extracted are formed by using mask patterns 44defining the gate electrode of a peripheral circuit and connected tofirst metal lines 48 via contact holes 47. The placement pitch of thecontrol gate electrodes 45 shaped like side spacers is the minimumdimension F. Since connection is impossible by using only the firstmetal lines 48, second metal lines 50 are also used via first connectionholes 49. The control gate electrodes 45 formed as side spacers on theperipheries of the trenched isolation regions 41 have been interruptedby mask patterns 46.

By the present embodiment, it has been shown that metal lines having aplacement pitch of the minimum dimension 2F can be connected to thecontrol gate electrodes 45 shaped like side spacers and having aplacement pitch of the minimum dimension F.

Embodiment 2 will further be described in detail with reference to FIGS.44 to 50. FIGS. 44 to 50 are diagrammatic plan views of the peripheralregion of the memory cell array portion in the flash memory shown inFIGS. 23 and 24 showing the manufacturing process steps therefor.

FIG. 44 shows a state in which insulating films 43 (multilayer films 9)used as the gate insulating films of the nonvolatile memory elementshave been formed on the semiconductor substrate including the topsurfaces of the rows of pillars 20. The insulating films 43 have beenformed on the semiconductor substrate in such as manner as to cover theside surfaces of the rows of pillars 20. For the sake of clarity, theportions of the insulating films 43 that have been formed on the sidesurfaces of the rows of pillars 20 and on the side surface of thetrenched isolation region 42 to surround the periphery of the memorycell array portion are depicted in FIG. 44. In FIGS. 23, 24, and 44 to50, the directions in which the rows of pillars 20 extend are shown in astate 90° shifted relative to FIG. 1.

As shown in FIG. 44, each of the rows of pillars 20 is constructed tohave the trenched isolation region 42 of a length along the direction inwhich the row of pillars 20 extends which is larger at the edge portionof the memory cell array than that of the insulator pillar 4 in themiddle portion. The trenched isolation regions 42 of the individual rowsof pillars 20 are formed such that every second of them is different inlength.

After the insulating film 43 shown in FIG. 44 is formed, a polysiliconfilm 10 is formed as a conductive film over the entire surface of thesemiconductor substrate including the top surfaces of the rows ofpillars 20, as shown in FIG. 45. Then, as shown in FIG. 45, the maskpatterns 44 are formed on the polysilicon film 10. The mask patterns 44have gate patterns for forming the gate electrode of a transistor for aperipheral circuit and extraction patterns (contact patterns) forforming the extracted regions (contact regions) of the word lines WLincluding the control gate electrodes 45 of the nonvolatile memoryelements. In short, the word lines WL including the control gateelectrodes 45 of the nonvolatile memory elements and extracted regions45 a are formed in the same process steps as the gate electrode of aMISFET composing the peripheral circuit.

Next, anisotropic etching such as RIE is performed with respect to thepolysilicon film 10 by using the mask patterns 44 as an etching mask,thereby forming the word lines WL shaped like side spacers and includingthe control gate electrodes 45 on the side surfaces of the rows ofpillars 20 and simultaneously forming the extracted regions 45 aintegrated with the word lines WL (control gate electrodes 45), as shownin FIGS. 46 and 47 (drawings showing a state in which the mask patternshave been removed). In this process step, the gate electrode of theMISFET composing the peripheral circuit is also formed. As for theformation of the word lines WL, including the control gate electrodes 45of the nonvolatile memory elements, the extracted regions 45 a, the gateelectrode of the MISFET composing the peripheral circuit, such formationwill be described with reference to the process steps illustrated inFIGS. 29 and 30 according to Embodiment 3, which will be describedlater.

Next, after the mask patterns 44 are removed as shown in FIG. 47, theword lines WL formed continuously on the side surfaces of the rows ofpillars 20 in such a manner as to surround the peripheries of the rowsof pillars 20 are partially removed by using the mask patterns 46 havingopenings 46 a. The partial removal of the word lines WL is performedunder etching conditions for selectively removing the word lines WL.

Next, after the mask patterns 44 are removed, an interlayer insulatingfilm is formed over the entire surface of the semiconductor substrateincluding the top surfaces of the rows of pillars 20, though this is notdepicted. Then, as shown in FIG. 49, the first metal lines 48 includingthe bit line BL, lines (48 a, 48 b), and the like are formed on theinterlayer insulating film. The bit lines BL are connected electricallyto the semiconductor regions (drain regions) provided on the surfaces ofthe semiconductor pillars 5 via the contact holes (connection holes) 47formed in the interlayer insulating film. The lines (48 a, 48 b) areconnected electrically to the extracted regions 45 a formed integrallywith the word lines WL via the contact holes (connection holes) 47formed in the interlayer insulating film.

Next, an interlayer insulating film is formed over the entire surface ofthe semiconductor substrate including the top surfaces of the firstmetal lines 48, though this is not depicted. Then, as shown in FIG. 50,the second metal lines 50 are formed on the interlayer insulating film.The second metal lines 50 are connected electrically to the lines 48 bvia the first connection holes (connection holes) 49 formed in theinterlayer insulating film.

In the present embodiment, the word lines WL including the control gateelectrodes 45 of the nonvolatile memory elements are formed on the sidesurfaces of the rows of pillars 20, while the extracted regions 45 aintegrated with the word lines WL are formed by performing anisotropicetching with respect to the polysilicon film 10 in the state in whichthe polysilicon film 10 is partially masked. By thus forming the wordlines WL and the extracted regions 45 a, the extremely fine word linesWL and the extracted regions 45 a integrated with the extremely fineword lines WL can be formed without an increase in the number ofmanufacturing process steps. In addition, the formation of the extractedregions 45 a integrated with the extremely fine word lines WL allowseasy electrical connection between the extremely fine word lines WL andlines in the upper layers.

In the present embodiment, the word lines WL including the control gateelectrodes of the nonvolatile memory elements have been formed as sidespacers on the side surfaces of the rows of pillars 20 as projectingisland regions in stripes by performing anisotropic etching with respectto the polysilicon film 10. Thus, the word lines WL are formedcontinuously in such a manner as to surround the peripheries of the rowsof pillars 20, resulting in a state in which the word line WL formed onone of the side surfaces of each of the rows of pillars 20 located onthe opposite sides (which are the side surface along the direction inwhich the semiconductor pillars 5 are arranged and the side surfacealong the longitudinal direction of the row of pillars) and the wordline WL formed on the other side surface are connected electrically toeach other. The word line WL formed on one of the two side surfaces ofeach of the rows of pillars 20 includes the control gate electrodes 45of the nonvolatile memory elements each using the one of the two sidesurfaces of the row of pillars 20 as the channel formation region, whilethe word line WL formed on the other side surface of the row of pillars20 includes the control gate electrodes of the nonvolatile memoryelements each using the other side surface of the row of pillars 20 asthe channel formation region.

When the word lines WL including the control gate electrodes 45 of thenonvolatile memory elements are formed as side spacers on the sidesurfaces of the rows of pillars 20 composed of projecting island regionsin stripes, each defined by the four side surfaces, it is necessary topartially remove the word lines WL after the formation thereof andthereby provide electrical isolation between the control gate electrodesof the nonvolatile memory elements using one of the side surfaces ofeach of the rows of pillars 20 as the channel formation regions and thecontrol gate electrodes of the nonvolatile memory elements using theother side surface of the row of pillars 20 as the channel formationregions, as has been performed in the present embodiment. In the presentembodiment, the word lines WL are partially removed from the trenchedisolation regions 42 at the edge portions of the rows of pillars 20, asshown in FIG. 48.

EMBODIMENT 3

The present embodiment pertains to a method of manufacturing memorycells according to the present invention and the transistor for theperipheral circuit in the same manufacturing process steps, which willbe described with reference to the cross-sectional views in theindividual manufacturing process steps shown in FIGS. 25 to 33. Each ofthe cross-sectional views shows a cross section of a peripheral circuitportion and a memory cell portion.

First, FIG. 25 shows a state in which a trenched isolation region 52 isformed by filling an oxide film in a trench at a depth of 250 nm in asurface region of a p-type semiconductor silicon substrate (hereinaftersimply referred to as a silicon substrate) 51 with a resistivity of 10Ωcm and planarizing it by CMP (Chemical Mechanical Polishing), and,then, a surface oxide film 53 with a thickness of 10 nm is formed.Through the surface oxide film 53, an n-type well region has been formedby implanting phosphorus ions at an acceleration energy of 1 MeV and animplant dose of 1×10¹³/cm², implanting phosphorus ions at anacceleration energy of 500 keV and an implant dose of 3×10¹²/cm², andimplanting phosphorus ions at an acceleration energy of 150 keV and animplant dose of 1×10¹²/cm², while a p-type well region has been formedby implanting boron ions at an acceleration energy of 500 keV and animplant dose of 1×10¹³/cm², implanting boron ions at an accelerationenergy of 150 keV and an implant dose of 5×10¹²/cm², and implantingboron ions at an acceleration energy of 50 keV and an implant dose of1×10¹²/cm², though they are not depicted.

Next, as shown in FIGS. 26 and 27, the portions of the silicon substrate51 in the memory cell region are etched to a depth of 250 nm to formrectangular parallelepiped silicon pillars (semiconductor pillars) 55 byusing resist patterns 54 as a mask and the portion of the oxide film intrenched isolation region 52 is etched subsequently. It is to be notedthat the etching of the oxide film is performed under conditions underwhich silicon is less likely to be etched.

Since the portion of the oxide film in the trenched isolation region 52has thus been etched after forming the silicon pillars 55 by etchingsilicon, the cutting away of the silicon substrate 51 under the trenchedisolation region 52 can be prevented. In addition, source regions areformed by implanting phosphorus ions at an acceleration energy of 50 keVand an implant dose of 2×10¹⁵/cm² by using the resist patterns 54 as amask.

FIG. 28 shows a state in which an oxide film 57 with a thickness of 5 nmand a nitride film 58 with a thickness of 10 nm have further beendeposited by CVD after the removal of the resist patterns 54 and thenthe portions of the nitride film 58 and the oxide film 57 in theperipheral circuit region have been etched by using a resist pattern 59covering the memory cell region as a mask.

Subsequently, the resist pattern 59 is removed and the surface oxidefilm 53 is removed by wet etching, as shown in FIG. 29. Then, gateoxidation for the transistor for the peripheral circuit is performed togrow a gate oxide film 60 with a thickness of 14 nm. Thereafter, anoxide film 61 with a thickness of 4 nm is deposited by CVD and apolysilicon film 62 doped with phosphorus at a concentration of1×10²⁰/cm³ and having a thickness of 80 nm is deposited subsequently.

Next, FIG. 30 shows a state in which processing for forming controlgates 65 shaped like side spacers, a control gate connecting region 66,and a peripheral gate 64 has been performed by etching the polysiliconfilm 62 by using, as a mask, resist patterns 63 for defining the gateelectrode of the transistor for the peripheral circuit.

Next, as shown in FIG. 31, the source and drain region 67 and 68 of theperipheral transistor and the drain regions 69 of the memory cells areformed by implanting arsenic ions at an acceleration energy of 30 keVand an implant dose of 2×10¹⁵/cm². Then, an oxide film 70 with athickness of 40 nm and a nitride film 71 with a thickness of 60 nm aredeposited by CVD and an oxide film 72 is further deposited by CVD andplanarized by CMP to a thickness of 700 nm. By using resist patterns 73for forming contact holes as a mask, etching is performed with respectto the oxide film 72 under etching conditions having a selectivity tothe nitride film, thereby forming contact holes 74 for the peripheralcircuit and contact holes 75 for the memory cell regions.

FIG. 32 shows a subsequent state in which the resist patterns 73 areremoved after etching the portions of the nitride film 71 and the oxidefilm 70 at the bottom portions of the contact holes 74 and 75, thecontact holes 74 and 75 are filled with tungsten plugs 76 formed bysputtering and CVD and planarized by CMP, and first metal lines 77 eachcomposed of a tungsten film with a thickness of 300 nm are formed.

Finally, as shown in FIG. 33, a first interlayer oxide film 78 with athickness of 500 nm is deposited by CVD, a first connection plug 79 isformed, and then a second metal line 80 composed of an aluminum filmwith a thickness of 500 nm is formed. Further, the process steps ofdepositing a second interlayer insulating film, forming a secondconnection plug, forming a third metal line, depositing a passivationfilm, and forming an opening in a bonding pad portion are performed,though they are not depicted, whereby the manufacturing process for theflash memory according to the present embodiment is completed.

Each of the nonvolatile memory cells according to the present embodimenthas been designed to have a minimum dimension of F=0.25 μm and a cellarea of 2F²=0.125 μm².

A write operation to the nonvolatile memory cell according to thepresent embodiment was performed by applying 5 V to the bit line andapplying a pulse voltage of 8 V to the control gate electrode with apulse width of 1 μs and the threshold voltage was raised from 2 V to 4V. On the other hand, an erase operation was performed by applying 6 Vto the bit line and applying a pulse voltage of −8 V to the control gateelectrode with a pulse width of 50 ms in the state in which thepotential at the source region is open and the threshold voltage waslowered successfully from 4 V to 2 V. After performing 100,000 rewriteoperations under the write/erase voltage conditions described above,variations in threshold voltage after writing and erasing were 0.4 V orless. Variations caused by rewriting in the properties of the memorycell were suppressed successfully to a 1.2-fold increase in write time,a 3-fold increase in erase time, and a 0.8-fold reduction in readcurrent. In a read operation involving the application of 1 V to the bitline and 3 V to the control gate, a read current having a sufficientlylarge value of 25 μA was obtained successfully, which proved theeffectiveness of the present invention.

EMBODIMENT 4

In the present embodiment, the multilayer film composing the gateinsulating film of the memory cell in Embodiment 3 described above andconsisting of the oxide film 57 with a thickness of 5 nm, the nitridefilm 58 with a thickness of 10 nm, and the oxide film 61 with athickness of 5 nm was changed to an oxide film 57 with a thickness of 4nm, a non-doped polysilicon film 81 with a thickness of 3 nm, a nitridefilm 58 with a thickness of 5 nm, and an oxide film 61 with a thicknessof 5 nm, as shown in the cross-sectional view of FIG. 34. In contrast tothe first embodiment in which the electron trap region is in the nitridefilm 58 with a thickness of 10 nm, the present embodiment primarily usesan interfacial trap between the non-doped polysilicon film 81 with athickness of 3 nm and the nitride film 58 with a thickness of 5 nm asthe charge accumulation region.

A plan view of memory cells according to the present embodiment is shownin FIG. 35, in which channel regions, oxide films 83 (57) each having athickness of 4 nm, the non-doped polysilicon films 81 each having athickness of 3 nm, nitride films 84 (58) each having a thickness of 5nm, and oxide films 85 (61) each having a thickness of 5 nm are stackedin layers on the side surface portions of the rectangular-parallelepipedsemiconductor pillars 55 which are dielectrically isolated from eachother by rectangular parallelepiped trenched isolation regions(insulator pillars) 82, control gates 86 each composed of a polysiliconfilm with a thickness of 70 nm are disposed as side spacers, and contactholes 87 to the drain regions and bit lines 88 are disposed on the uppersurface regions of the rectangular-parallelepiped semiconductor pillars55.

Cross sections along the C–C′ and D–D′ directions shown in FIG. 35 areshown in FIGS. 36( a) and 36(b), respectively. In the cross sectionalong the C–C′ direction, oxide films 94 (83) each having a thickness of4 nm, non-doped polysilicon films 102 (81) each having a thickness of 3nm, nitride films 95 (84) each having a thickness of 5 nm, and oxidefilms 96 (85) each having a thickness of 5 nm are stacked in layers overthe surface region of a p-type semiconductor substrate 91 (51) with aresistivity of 10 Ωcm and the side surface portions of a semiconductorpillar 101 (55) configured as a rectangular parallelepiped of 0.25 μm,followed by control gates 97 (86) each composed of a polysilicon filmwith a thickness of 70 nm and disposed as side spacers such that theouter circumference is covered successively therewith, while sourceregions 92 (56) are disposed in the lower portions of therectangular-parallelepiped semiconductor pillars 101 (55) and a drainregion 93 (69) is disposed in the upper portion thereof. In the crosssection along the D–D′ direction, the rectangular-parallelepipedsemiconductor pillars 101 are isolated by insulating films 98 and thedrain region 93 is connected to bit lines 100 with line widths and linespacings of 0.25 μm via contact plugs 99.

Each of the nonvolatile memory cells according to the present embodimenthas been designed to have a minimum dimension of F=0.25 μm and a cellarea of 2F²=0.125 μm².

In a write operation to the nonvolatile memory cell according to thepresent embodiment, hot electrons were injected by applying 5 V to thebit line and applying a pulse voltage of 8 V to the control gateelectrode with a pulse width of 1 μs to be trapped in the interfacebetween the non-doped polysilicon film 102 and the nitride film 95 sothat the threshold voltage was raised from 2 V to 4 V. On the otherhand, an erase operation was performed by applying 5 V to thesemiconductor substrate 91 and applying a pulse voltage of −8 V to thecontrol gate electrode with a pulse width of 10 ms in the state in whichthe potential at the source region is open so that the trapped electronsare detrapped into the non-doped polysilicon film 102 and then extractedto the semiconductor substrate 91 by using a tunnel current flowing inthe oxide film 94.

After performing 100,000 rewrite operations to the nonvolatile memorycell according to the present embodiment under the write/erase voltageconditions described above, variations in threshold voltage afterwriting and erasing were as excellent as 0.2 V or less. Variationscaused by rewriting in the properties of the memory cell were suppressedsuccessfully to a 1.2-fold increase in write time, a 3-fold increase inerase time, and a 0.9-fold reduction in read current. In a readoperation involving the application of 1 V to the bit line and 3 V tothe control gate, a read current having a sufficiently large value of 25μA was obtained successfully, which proved the effectiveness of thepresent invention.

EMBODIMENT 5

Of the oxide film 57 with a thickness of 4 nm, the non-doped polysiliconfilm 81 with a thickness of 3 nm, the nitride film 58 with a thicknessof 5 nm, and the oxide film 61 with a thickness of 5 nm composing thegate insulating film of the memory cell in Embodiment 3, the non-dopedpolysilicon film 102 with a thickness of 3 nm was changed to non-dopedpolysilicon grains 103 each having a diameter of 4 nm in the presentembodiment, as shown in FIG. 37. The average diameter of the non-dopedpolysilicon grains 103 was 4 nm, the average spacing thereof was 5 nm,and the effective surface density thereof was 1.2×10¹² cm⁻².

In a write operation to the nonvolatile memory cell according to thepresent embodiment, hot electrons were injected by applying 5 V to thedrain region 69 and applying a pulse voltage of 8 V to the control gateelectrode 65 with a pulse width of 1 μs to be trapped in the interfacebetween each of the non-doped polysilicon grains 103 and the nitridefilm 58 so that the threshold voltage was raised from 2 V to 5 V, in thesame manner as in the case of Embodiment 3. On the other hand, an eraseoperation was performed by applying 5 V to the semiconductor siliconsubstrate (semiconductor substrate) 51 and applying a pulse voltage of 8V to the control gate electrode 65 with a pulse width of 50 ms in thestate in which the potential at the source region 56 is open so that thetrapped electrons are detrapped into the non-doped polysilicon grains103 and then extracted to the semiconductor substrate 51 by using atunnel current flowing in the oxide film 57.

EMBODIMENT 6

In a structure according to the present embodiment, the nitride film 58composing the gate insulating film of the memory cell in Embodiment 5 isnot provided as shown in FIG. 38.

EMBODIMENT 7

Of the oxide film 57 with a thickness of 5 nm, the nitride film 58 witha thickness of 10 nm, and the oxide film 61 with a thickness of 5 nmcomposing the gate insulating film of the memory cell in Embodiment 3described above, the nitride film 58 was replaced with a metal oxidefilm in the present embodiment. As the metal oxide film, ditantalumpentaoxide (Ta₂O₅), alumina (Al₂O₃), titanium oxide (Ti₂), zirconiumoxide (ZrO₂), hafnium oxide (HfO₂), or the like can be used providedthat the film thickness is optimized depending on the individualdielectric constants thereof.

Although the invention achieved by the present inventor has beendescribed specifically based on various embodiments thereof, the presentinvention is not limited thereto. It will easily be appreciated thatvarious changes and modifications can be made in the invention withoutdeparting from the gist thereof.

The following is a brief description of effects achievable by arepresentative aspects of the invention disclosed in the presentapplication.

In accordance with the present invention, a read current for anonvolatile memory using a nonconductive charge trap film as a chargeaccumulation region can be improved significantly and there can beprovided a semiconductor integrated circuit device capable ofeliminating a read failure due to data inversion caused by read disturb.

In accordance with the present invention, there can be provided a devicestructure which allows easy reduction of the cell area of thenonvolatile memory using the nonconductive charge trap film as thecharge accumulation region.

In accordance with the present invention, a semiconductor integratedcircuit device having nonvolatile memory elements to which electricalwriting and erasing of data can be performed can be improved in electricreliability.

Thus, the semiconductor integrated circuit device according to thepresent invention is useful as a semiconductor product to beincorporated into electronic equipment and is particularly useful as asemiconductor memory to be incorporated into mobile electronic equipmentsuch as a memory card or mobile phone.

1. A semiconductor integrated circuit device comprising electricallywritable nonvolatile memory elements each including, in a semiconductorregion: a source region; a drain region; a channel formation regioninterposed between said source region and said drain region; and acontrol gate electrode, wherein two of said channel formation regionsare disposed independently over respective opposing side surfaces ofeach of rectangular-parallelepiped semiconductor pillars, said drainregion connected to said two channel formation regions is formed in anupper portion of said rectangular-parallelepiped semiconductor pillar,each of a plurality of insulator pillars is disposed between adjacentones of said semiconductor pillars to form a row such that said channelforming regions are not faced toward side surfaces of said insulatorspillars, a first insulating film is provided between each of saidchannel formation regions and said control gate electrode, anonconductive charge trap film is provided over said first insulatingfilm, and a second insulating film is provided over said nonconductivecharge trap film.
 2. A semiconductor integrated circuit device accordingto claim 1, wherein writing is performed by placing said source regionat a ground potential, giving a proper positive potential to each ofsaid drain region and said control gate electrode to turn ON saidchannel formation regions, and injecting hot electrons generated in thevicinity of said drain region such that the electrons are trapped insaid nonconductive charge trap film, and wherein erasing is performed bygiving a proper negative potential and a proper positive potential tosaid control gate electrode and said drain region, respectively, andthereby extracting the electrons trapped in said nonconductive chargetrap film to said semiconductor region by using a tunnel current flowingin said first insulating film.
 3. A semiconductor integrated circuitdevice according to claim 1, wherein said first insulating film is asilicon oxide film, said nonconductive charge trap film is a siliconnitride film, and said second insulating film is a silicon oxide film.4. A semiconductor integrated circuit device according to claim 1,wherein said first insulating film is a silicon oxide film, saidnonconductive charge trap film is a metal oxide film, and said secondinsulating film is a silicon oxide film.
 5. A semiconductor integratedcircuit device comprising electrically writable nonvolatile memoryelements each including, in a semiconductor region: a source region; adrain region; a channel formation region interposed between said sourceregion and said drain region; and a control gate electrode, wherein twoof said channel formation regions are disposed independently overrespective opposing side surfaces of each of rectangular-parallelepipedsemiconductor pillars, said drain region connected to said two channelformation regions is formed in an upper portion of saidrectangular-parallelepiped semiconductor pillar, each of a plurality ofinsulator pillars is disposed between adjacent ones of saidsemiconductor pillars to form a row such that said channel formingregions are not faced toward side surfaces of said insulators pillars, afirst insulating film is provided between each of said channel formationregions and said control gate electrode, a semiconductor film isprovided over said first insulating film, a nonconductive charge trapfilm is provided over said first insulating film, a second insulatingfilm is provided over said nonconductive charge trap film, and electronsare trapped primarily in a charge trap level at an interface betweensaid semiconductor film and the nonconductive charge trap film.
 6. Asemiconductor integrated circuit device according to claim 5, whereinwriting is performed by placing said source region at a groundpotential, giving a proper positive potential to each of said drainregion and said control gate electrode to turn ON said channel formationregions, and injecting hot electrons generated in the vicinity of saiddrain region such that the electrons are trapped primarily in a chargetrap level at an interface between said semiconductor film and saidnonconductive charge trap film, and wherein erasing is performed bygiving a proper negative potential and a proper positive potential tosaid control gate electrode and said drain region, respectively, andthereby extracting the trapped electrons to said semiconductor region byusing a tunnel current flowing in said semiconductor film and the firstinsulating film.
 7. A semiconductor integrated circuit device accordingto claim 5, wherein said first insulating film is a silicon oxide film,said semiconductor film is a polysilicon film, said nonconductive chargetrap film is a silicon nitride film, and said second insulating film isa silicon oxide film.
 8. A semiconductor integrated circuit deviceaccording to claim 5, wherein said first insulating film is a siliconoxide film, said semiconductor film is a polysilicon film, saidnonconductive charge trap film is a metal oxide film, and said secondinsulating film is a silicon oxide film.
 9. A method for manufacturing asemiconductor integrated circuit device, comprising at least the stepsof: alternately forming, over a semiconductor substrate, trenchedisolation regions, each comprised of insulator material, andsemiconductor active regions, each comprised of a semiconductormaterial, in stripes, performing etching with respect to saidsemiconductor active regions and said trenched isolation regions instripes in directions orthogonal to said trenched isolation regions andsemiconductor active regions in stripes to formrectangular-parallelepiped semiconductor pillars andrectangular-parallelepiped insulator pillars such that each of insulatorpillars is disposed between adjacent ones of said semiconductor pillarsto form a row; forming channel formation regions in respective sidesurface portions of each of said rectangular-parallelepipedsemiconductor pillars, depositing a multilayer film comprised of a firstoxide film, a nitride film, and a second oxide film over each of saidchannel formation regions, and forming word lines comprised of sidespacers each made of a conductive film; and forming a drain region in anupper portion of each of said rectangular-parallelepiped semiconductorpillars.
 10. A method for manufacturing a semiconductor integratedcircuit device, comprising at least the steps of: alternately forming,over a semiconductor substrate, trenched isolation regions, eachcomprised of insulator material, and semiconductor active regions, eachcomprised of a semiconductor material, in stripes, performing etchingwith respect to said semiconductor active regions and said trenchedisolation regions in stripes in directions orthogonal to said trenchedisolation regions and semiconductor active regions in stripes to formrectangular-parallelepiped semiconductor pillars andrectangular-parallelepiped insulator pillars, such that each of saidinsulator pillars is disposed between adjacent ones of saidsemiconductor pillars to form a row; forming channel formation regionsin respective side surface portions of each of saidrectangular-parallelepiped semiconductor pillars, depositing amultilayer film comprised of a first oxide film, a polysilicon film, anitride film, and a second oxide film over each of said channelformation regions, and forming word lines comprised of side spacers eachmade of a conductive film; and forming a drain region in an upperportion of each of said rectangular-parallelepiped semiconductorpillars.
 11. A method of manufacturing a semiconductor integratedcircuit device, comprising steps of: forming a conductive film coveringprojecting island regions which are formed in stripes and regionsadjacent to said projecting island regions, wherein an insulating filmis formed between said projecting island regions and said conductivefilm; and performing anisotropic etching to said conductive film byusing a mask covering contact regions to be formed from said conductivefilm so as to form conductive lines on side surfaces of said projectingisland regions and said contact regions integrated with said conductivelines.
 12. A method of manufacturing a semiconductor integrated circuitdevice according to claim 11, wherein said anisotropic etching isperformed so as to form an electrode of a peripheral circuit element ina peripheral circuit forming region by using said mask.
 13. A method ofmanufacturing a semiconductor integrated circuit device according toclaim 11, wherein said insulating film includes a film for discretelyaccumulating charge therein, and wherein each said conductive lineserves as a gate electrode of a nonvolatile memory element and has ashape of a side wall spacer formed in self-alignment to said sidesurface of a corresponding one of said projecting island regions.
 14. Amethod of manufacturing a semiconductor integrated circuit device,comprising steps of: forming a conductive film covering projectingisland regions which are formed in stripes and regions adjacent to saidprojecting island regions; wherein an insulating film is formed betweensaid projecting island regions and said conductive film; and performinganisotropic etching to said conductive film by using a mask coveringcontact regions to be formed from said conductive film so as to formconductive lines on side surfaces of said projecting island regions andsaid contact regions integrated with said conductive lines, wherein saidanisotropic etching is performed so as to form an electrode of aperipheral circuit element in a peripheral circuit forming region byusing said mask, wherein said insulating film includes a film fordiscretely accumulating charge therein, and wherein each of saidconductive lines serves as a gate electrode of a nonvolatile memoryelement and has a shape of a side wall spacer formed in self-alignmentto said side surface of a corresponding one of said projecting islandregions.
 15. A method of manufacturing a semiconductor integratedcircuit device, comprising steps of: forming a conductive film coveringprojecting island regions each extending in a first direction such thatan insulating film is formed between said projecting island regions andsaid conductive film; performing anisotropic etching to said conductivefilm so as to form conductive lines on side surfaces of said projectingisland regions such that each of said conductive lines serves as a gateelectrode of an element and has a shape of a side wall spacer formed inself-alignment to said side surface of a corresponding one of saidprojecting island regions; and after said anisotropic etching step,partially removing said conductive lines adjacent in a second directioncrossing to said first direction by using a mask extending over saidprojecting island regions adjacent in said second direction.
 16. Amethod of manufacturing a semiconductor integrated circuit deviceaccording to claim 15, wherein said insulating film includes a film fordiscretely accumulating charge therein, and wherein said elements arenonvolatile memory elements.
 17. A method of manufacturing asemiconductor integrated circuit device according to claim 15, whereinsaid conductive film is also formed to cover regions adjacent to saidprojecting island regions and said anisotropic etching is performed byusing a mask covering contact regions to be formed from said conductivefilm so as to form conductive lines on side surfaces of said projectingisland regions and said contact regions integrated with said conductivelines.
 18. A method of manufacturing a semiconductor integrated circuitdevice according to claim 15, wherein said anisotropic etching isperformed so as to form an electrode of a peripheral circuit element ina peripheral circuit forming region by using said mask.
 19. A method ofmanufacturing a semiconductor integrated circuit device according toclaim 11, further comprising, after said anisotropic etching step,partially removing said conductive lines adjacent in a directioncrossing to said stripes by using a mask extending over said projectingisland regions in said direction.
 20. A method of manufacturing asemiconductor integrated circuit device according to claim 11, whereinsaid mask is formed to over a region covering said contact region and apart of said conductive line such that said contact region is integratedwith said conductive line.
 21. A method of manufacturing a semiconductorintegrated circuit device according to claim 11, further comprising thesteps of: forming an insulated film over said conductive lines and saidcontact regions, forming openings in said insulating film, and formingplugs in said openings such that plugs are electrically connected tosaid contact regions.
 22. A method of manufacturing a semiconductorintegrated circuit device according to claim 11, wherein said conductiveline serves as a word line and has a shape of a side wall spacer formedin self-alignment to said side surface of said projecting island region.23. A method of manufacturing a semiconductor integrated circuit deviceaccording to claim 14, wherein said mask is formed to over a regioncovering said contact region and a part of said conductive line suchthat said contact region is integrated with said conductive line.
 24. Amethod of manufacturing a semiconductor integrated circuit deviceaccording to claim 15, wherein said mask is formed to over a regioncovering said contact region and a part of said conductive line suchthat said contact region is integrated with said conductive line.
 25. Amethod of manufacturing a semiconductor integrated circuit deviceaccording to claim 15, further comprising the steps of: forming aninsulating film over said conductive lines and said contact regions,forming openings in said insulating film, and forming plugs in saidopening such that said plugs are electrically connected to said contactregions said contact regions.
 26. A method of manufacturing asemiconductor integrated circuit device according to claim 15, furthercomprising the steps of: forming an insulating film over said conductivelines and said contact regions, forming openings in said insulatingfilm, and forming plugs in said openings such that said plugs areelectrically connected to said contact said contact regions.